1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the encoding of memory bus addresses within data processing systems.
2. Description of the Prior Art
Off-chip memory bus connections tend to be physically larger and have a higher capacitance than on-chip memory bus lines. Accordingly, it consumes a disadvantageous amount of energy to drive such memory buses.
It is known to encode addresses on memory buses so as to reduce to Hamming distance between consecutive addresses. An example of such a technique is described in the paper “Low Power Techniques for Address Encoding And Memory Allocation” by Wei-Chung Cheng et al, Proceedings of the 2001 Conference on Asia South Pacific Design Automation Pages 245-250. By reducing the number of transitions which occur on the memory bus lines in the course of sequential memory accesses, such techniques reduce the energy consumed. Statistically sequential accesses are likely and accordingly such an encoding which reduces the Hamming distances for sequential accesses is advantageous and justifies the additional circuits required to perform the encoding.
A feature of some memory devices (e.g. SDRAM) is the ability to support burst mode transfers. When operating in burst mode such devices will receive a starting memory address and then return or write to a sequence of data values stored at locations following on from that starting address. The number of data values in the sequence may be set by a programmable burst length parameter. As an example, an SDRAM device which has been configured with a burst length of eight bytes would respond to a data read from a memory address by returning eight data values starting at that memory address and following on from that memory address.